MOS Photo Sensitivity

Light Source
Amplitude
Calculations

For a p-type substrate under positive VG, bands bend downward at the oxide-semiconductor interface and surface potential φs increases.

Weak inversion — φF < φs < 2φF. Ei crosses below EF at the surface, so ns = ni·exp(qφs/kT) exceeds ni but is still ≪ NA. Sparse minority carriers, depletion width still growing with VG.

Strong inversion — φs = 2φF. Now ns = NA: the surface is as n-type as the bulk is p-type. The inversion layer screens further VG — all additional voltage drops across the oxide. Depletion width pins at:

Wmax = √(2εs·2φF / qNA)

Deep depletion — if VG is pulsed beyond threshold faster than thermal generation can fill the inversion layer (τgen ~ ms), φs > 2φF and W > Wmax. This non-equilibrium state is where the MOS cap is most photosensitive, and is the operating regime of every CCD pixel.

Accumulation (VG < VFB) — majority carriers at surface, no depletion, no field. Photogenerated pairs recombine. Essentially zero photoresponse.

Depletion (VFB < VG < VT) — W grows as √φs. Photons absorbed within W or within one diffusion length L of the depletion edge generate e-h pairs swept by the field. Electrons → surface, holes → bulk. Sensitivity grows with VG.

Strong inversion (equilibrium) — W pinned at Wmax. Moderate but capped sensitivity. Inversion layer screens additional gate voltage.

Deep depletion (pulsed VG ≫ VT) — maximum sensitivity. W ≫ Wmax, no inversion layer to screen the field. Photogenerated electrons drifting to the surface are the inversion charge — photons do the work thermal generation would eventually do.

Practical consequence: pulse VG high → integrate photo-charge → read out before dark current fills the well. That’s the CCD clock cycle.

Two properties dominate: bandgap sets the long-λ cutoff (λmax = hc/Eg), and absorption coefficient α(λ) determines required depletion width for efficient collection.

MaterialEgχλcutGapNotes
GaN3.40 eV4.10 eV365 nmDirectUV-selective
4H-SiC3.26 eV3.17 eV380 nmIndirectUV, rad-hard
GaAs1.42 eV4.07 eV873 nmDirectα ~ 10⁴ cm⁻¹ at edge
InP1.34 eV4.38 eV925 nmDirectTelecom substrate
Si1.12 eV4.05 eV1107 nmIndirectα ~ 10² cm⁻¹ at edge
In₀.₅₃Ga₀.₄₇As0.74 eV4.50 eV1676 nmDirectC+L telecom
Ge0.66 eV4.00 eV1879 nmIndirectSWIR

Direct bandgap (GaAs, InP, GaN, InGaAs): sharp absorption onset, α ~ 10⁴ cm⁻¹ at edge — 1 μm depletion captures most photons. Indirect (Si, Ge, SiC): phonon-assisted, α ~ 10² cm⁻¹ near Eg, needing 10–100 μm depletion for long-λ collection → low doping or deep depletion.

Short-λ cutoff: oxide transparency and surface recombination. SiO₂ transparent to ~150 nm. High-κ (HfO₂) absorbs below ~250 nm. Blue/UV has very high α → absorbed in first ~10 nm where S₀ is high → kills blue QE unless BSI.

Electron affinity χ sets the vacuum level offset E₀ = Ec + χ. Toggle “E₀ vacuum” to see how χ scales with material — notice 4H-SiC’s unusually small χ (3.17 eV), which is why SiC is attractive for electron emission and NEA devices.

Junction origin — PN diode has a built-in junction with φbi; depletion exists at equilibrium and widens with reverse bias. MOS cap depletion is entirely voltage-induced — no junction.

Operating mode — PN: steady-state, DC reverse bias, continuous photocurrent Jph = qGW + diffusion terms. MOS cap: integrating detector in deep depletion (non-equilibrium). Photo-charge accumulates in surface potential well; must be clocked out. Current-mode vs charge-mode.

Speed — PN/PIN bandwidth set by τtr = W/vsat and RC. GHz-capable. MOS cap “bandwidth” = integration time + charge transfer rate. Fine for video-rate imaging, not for telecom.

Dark current — both have Jdark ~ qniW/τg. MOS cap in deep depletion has W > Wmax → worse dark current at equal doping/temperature. CCDs need cooling for long exposures.

QE — comparable at similar W. Deep depletion can exceed PN QE at long λ because W > Wmax → larger collection volume.

Bottom line — PN = continuous current source → TIA → real-time sensing. MOS cap = charge bucket → fill with photons → read out. PN wins for speed. MOS cap wins for imaging arrays: every pixel is just a capacitor (compact, scalable, integrating). This is why CCDs worked and why CMOS APS still uses MOS depletion under the transfer gate — the 4T pixel architecture.